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Low-jitter reference-based synchronization for dual RF transmitters

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Parent Category: 2026

Category: Content №4 2026

Created on 24 August 2026

Last Updated on 24 August 2026

Published on 30 November -0001

Written by V. Ye. Sokol, P. Murr, T. L. Kurtseitov, R. V. Korolov

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Authors:

V. Ye. Sokol, orcid.org/0009-0009-9446-2049, National Technical University “Kharkiv Polytechnic Institute”, Kharkiv, Ukraine

P. Murr, orcid.org/0009-0007-4094-0223, International University of Science and Technology in Kuwait, Ardiya, Kuwait

T. L. Kurtseitov, orcid.org/0000-0001-6478-6469, National Defense University of Ukraine, Kyiv, Ukraine

R. V. Korolov*, orcid.org/0000-0002-7948-5914, National Technical University “Kharkiv Polytechnic Institute”, Kharkiv, Ukraine, e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

* Corresponding author e-mail: This email address is being protected from spambots. You need JavaScript enabled to view it.

повний текст / full article

Naukovyi Visnyk Natsionalnoho Hirnychoho Universytetu. 2026, (4): 164 - 173

https://doi.org/10.33271/nvngu/2026-4/164

Abstract:

Purpose. To develop a low-jitter synchronization unit for two radio transmitters based on a com-mon reference oscillator in 0.18 µm CMOS technology.

Methodology. The work utilizes circuit simulation methods in the MATLAB/Simulink environment using the bilinear z-transform to analyze the dynamics of Phase-Locked Loop (PLL) stages. The PCB layout design was carried out considering electrodynamic parameters (a target impedance of 50 ohms and FR-4 material) alongside RC parameter extraction to minimize phase skew. Experimental verification was conducted based on 0.18 µm CMOS technology.

Findings. A dual-loop architecture (consisting of a Clock and Data Recovery (CDR) block and a jitter filter) was created, ensuring signal stability at a frequency of 1.173 GHz. A phase noise level of -101.52 dBc/Hz at a 100 kHz offset and a root mean square (RMS) jitter of 3.3 ps for the synthesizer and 4.2 ps for the CDR node were achieved. The frequency lock time is 27.3 microseconds with a power consumption of 36 mW per node.

Originality. The use of an innovative charge pump architecture with an operational error amplifier is justified for precise potential equalization of nodes, which minimizes parasitic spurs and phase shift. For the first time, the integration of OR logic directly into the structure of the prescaler’s D-flip-flops has been proposed, eliminating additional signal propagation delays and reducing cumulative jitter.

Practical value. The proposed solution allows for the abandonment of complex software-based phase skew correction algorithms in Massive MIMO and SDR systems. The low jitter level (3.3 ps) enables the stable deployment of higher-order quadrature modulation schemes, including 256 QAM, thereby improving the error vector magnitude (EVM) and the efficiency of next-generation radio links.

Keywords: phase coherence, jitter, PLL, CDR, TCXO, prescaler, synchronization, beamforming

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